NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for a talented junior design engineer to join our silicon design team. The ideal candidate will be eager to learn cutting edge ASIC design technology and modern ASIC design flows. She/He will have the unique opportunity to get full support / education from our highly experienced ASIC design team in Belgrade. The team is responsible for critical aspects of Nextsilicon’s ASIC design. Come join Nextsilicon’s center of excellence, and have a big impact on our future products.

• Bachelor’s or Master’s degree or equivalent experience in Electrical or Computer Engineering
• 2-4 years experience in logic design and RTL coding in Verilog / SystemVerilog (ASIC or FPGA).
• Candidates with strong academic accomplishments could also be considered even with less experience.
• Must be familiar with ASIC design and verification processes, methodology and tools.
• Scripting experience (Python, Perl, TCL, shell programming) is an advantage
• A background in computer architecture, multi-core architecture, cache coherency, high speed memory subsystems or high speed interconnects is nice to have.
• Good written and verbal communication skills.
• Collaborative and team-oriented approach.

• Participate in integration of complex design subsystems.
• Responsibility for various flow elements and help make sure the design meets our challenging power and overall quality requirements.
• Designing new blocks for our HPC/AI products.