NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

NextSilicon is looking for a talented and experienced DFT Technical Manager to play a crucial role in the DFT implementation of the company’s next SOC. A Design for Test (DFT) Technical Engineering Manager plays a critical role in the semiconductor and electronics industries, focusing on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. The primary goal of a DFT Technical Manager is to develop flow/methodology for various DFT techniques in the design, manage junior DFT engineers and integrate test structures within the design of electronic components to facilitate efficient testing throughout the lifecycle of the product, from production to deployment and maintenance.

• At least 12 years of experience in DFT implementation / methodology is a must
• Strong understanding of digital design and test principles.
• Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion
• Experience with EDA tools (e.g., Synopsys DFT Compiler, Mentor Tessent) and scripting languages (e.g., Python, TCL).
• Knowledge of IC design flows, verification tools, and fault models
• Ability to identify, analyze, and resolve testing challenges.
• Work effectively within multidisciplinary teams, communicating complex technical details clearly.
• Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards.
• Technically lead/managed 3-4 junior DFT engineers to deliver DFT implementation on SOC
• Developed Flow/methodology for DFT in role as DFT Technical lead

• Hands on development of DFT flow/methodologies along with managing a team of 3-4 DFT engineers to implement DFT techniques on next generation of SOC
• Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, MBIST
• Implement and validate DFT features to ensure coverage and quality.
• Perform scan insertion, MBIST insertion and ensure architectural spec is met
• Generate ATPG patterns for stuck at and at speed, ensure all sequential elements are scannable to achieve high coverage. Generate MBIST patterns and ensure all memories are being covered for defects
• Collaborate with design teams to create test strategies and plans that identify potential defects
• Perform simulations and verification of DFT designs to confirm functionality and accuracy.
• Analyze fault models and optimize for high coverage, including stuck-at, transition, and path delay faults.
• Collaborate with test engineers to perform yield analysis and improve DFT methodologies.
• Troubleshoot and debug design issues found during testing.
• Develop techniques to isolate faults and improve test coverage with minimal impact on design.
• Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively.
• Document DFT architecture, procedures, and test coverage to support production testing and ongoing improvement.